This invention relates to programmable logic devices (“PLDs”), especially field programmable logic devices, which are often called field programmable gate arrays or FPGAs. More particularly, the invention relates to methods for producing configuration data for an FPGA that will make the FPGA function as a close operational equivalent to a structured ASIC that has been designed to implement logic desired by a user.
Chua et al. U.S. patent application Ser. No. 10/884,460, filed Jul. 2, 2004, shows examples of structured, application-specific, integrated circuits (“structured ASICs”) that can be fabricated to perform logic that may have been initially implemented in an FPGA to which the structured ASIC is somewhat structurally related. The Chua et al. ASICs are said to be structured because they include some basic logic circuit building blocks or units that can be made to perform various functions by customizing only a subset of the masks used to make the ASIC. These basic ASIC building blocks can also be interconnected in many different ways, again by customizing only a subset of the masks used to make the ASIC. The ASIC building blocks are not one-for-one equivalents to the basic building blocks or units in the related FPGA, but functions performed by an FPGA building block can generally be provided in the ASIC by one or a relatively small number of adjacent or nearby ASIC building blocks. This approach facilitates the design of an ASIC for performing logic that may have been initially implemented in an FPGA. For example, the number of ASIC masks that have to be customized is reduced, which lowers ASIC design cost, speeds the ASIC design process, and reduces the risk that the ASIC will not perform as desired (e.g., as a close operational equivalent to a related FPGA performing the same logic). Using ASIC building blocks that are less than one-for-one equivalents of FPGA building blocks, but that can be clustered (if necessary) to perform the functions of an FPGA building block, allows the ASIC to use only as many of its building blocks as are necessary to implement the functions of each FPGA building block. Because most logic designs use only some of the full functionality of each FPGA building block, this generally allows the ASIC to be smaller than it would be if its building blocks were each as fully featured as an FPGA building block.
The Chua et al. reference includes some technology related to providing FPGA and ASIC implementations of a user's logic that are close operational equivalents of one another. Yuan et al. U.S. patent application 10/916,305, filed Aug. 11, 2004, provides additional technology related to converting a user's FPGA logic to ASIC logic that is a close operational equivalent. The advantages of this type of technology are great. Some of those advantages are identified above. Improvements, extensions, and enhancements are therefore always sought.